Speaking at a Memory Executive Summit in Taipei ahead of SEMICON Taiwan, Samsung's memory product planning head Choi Jang-seok laid out a 3D memory roadmap the company brands CUBE — capacity, utilisation, bandwidth, efficiency. The headline numbers are large. None of them describe a product you can buy.
The roadmap as stated
HBM5: twice the performance of HBM4E, +20% performance per watt, −20% thermal resistance. zHBM: 8x HBM4E performance, 3x per watt, and a claimed 75–90% reduction in thermal resistance, achieved by stacking the memory directly on the logic die rather than beside it. zNAND-O: four or eight V-NAND dies through TSV, 10x the bit density of DRAM and 7x the read bandwidth of conventional NAND, sampling from 2028.
What the framing gets wrong
Two errors are already in circulation. The first is tense: these are targets. HBM5 mass production is placed around 2028 and zHBM after 2029; "Samsung launches HBM5" is false. The second is the baseline. Every multiplier is stated against HBM4E — a part that is itself not in volume production. "Eight times faster than today's memory" is therefore not what was said, because today's memory is HBM3E and HBM4.
What the strategy actually claims
Choi's line — that Samsung "will no longer be constrained by the printed circuit board area" — is the substance. Stacking memory on top of logic is a packaging and geometry argument, not processing-in-memory: the compute does not move into the DRAM. It does, however, put Samsung in direct competition for the base die, the layer SK hynix is customising and TSMC is packaging.
Context worth keeping
Korea Herald notes DRAM accounted for 39% of Samsung's second-quarter revenue and NAND 29.3%. That is the business this roadmap defends. Some widely repeated specifics — a 2nm base die against 4nm for HBM4/HBM4E, stacks of 12, 16 and 20 layers — come from TrendForce rather than the Korean reports of the keynote, and should be attributed accordingly rather than folded into Samsung's own claims.