Yields on TSMC's 5.5-reticle CoWoS advanced packaging now consistently exceed 98% and reach roughly 99% in some cases, according to remarks by TSMC vice-president Jun He reported on 11 August.
Why reticle count is the ceiling
A reticle is the maximum area a lithography tool can expose in one shot. Advanced packaging stitches multiple reticle-sized regions onto a single substrate, and every additional one multiplies the chance of a defect killing an assembly already carrying several finished dies. A 98% yield at 5.5 reticles means the most expensive assemblies in the industry are no longer the risky step.
The 2028 target
TSMC maps a 14-reticle package for 2028, integrating around 10 compute dies with 20 HBM stacks, with formats beyond that from 2029. That is roughly triple today's area budget, and it sets the physical envelope accelerator designers can plan against.
Capacity and interconnect
CoWoS capacity has nearly doubled each year for three consecutive years, across ten advanced packaging facilities. On the SoIC side, hybrid bond pitch tightens from 6µm in 2025 to 4.5µm by 2029 — around 50x the interconnect density.
What TSMC says is short
He flagged memory and ABF substrates, not packaging capacity, as the AI bottlenecks. Note the sourcing: these are reported remarks at a technical event relayed through Taiwanese press, not a TSMC release, and the 2028 roadmap is a plan rather than a product.
Why a 2028 number matters now
Accelerator architectures are locked years before tape-out, so a stated reticle budget for 2028 is a design input today. Ten compute dies against twenty HBM stacks implies memory bandwidth far beyond current parts — which is precisely why the bottleneck He names is memory and substrates rather than packaging capacity.