Cadence Design Systems reported second-quarter results after the US close on 27 July, beating estimates and raising full-year guidance on what chief executive Anirudh Devgan called "accelerating demand for our AI-driven solutions across both Design for AI and AI for Design fronts." The stock rose about 4% after hours.
The quarter
Revenue of $1.584 billion, up 24% from $1.275 billion. Non-GAAP diluted earnings per share of $2.11 against $1.65; GAAP EPS of $1.33 against $0.59. Non-GAAP operating margin 45.5%, GAAP 28.4%. Backlog reached a record $8.1 billion, with 12-month remaining performance obligations of $4.2 billion. Full-year guidance was raised to revenue of $6.26–6.34 billion, roughly 19% growth, with non-GAAP EPS of $8.05–8.15.
Where the growth actually sits
IP revenue grew more than 40% year on year, system design and analysis 37%, and core EDA 18%; the hardware emulation business added 12 new customers. Cadence also launched AuraStack, an AI "super agent" for printed circuit boards and advanced packaging, joining its ChipStack, ViraStack and InnoStack agents.
The line item that does not exist
Cadence does not break out AI revenue. The 24% figure is total revenue, and the fastest-growing components — IP and emulation — are driven by customers designing AI chips, which is a different business from customers buying AI features. The distinction matters when reading the agentic-AI positioning: that is a claim about product direction, not a disclosed number. Backlog is not revenue either, and includes multi-year contracts; the only figure with a 12-month horizon is the $4.2 billion cRPO.
Why this is a leading indicator
Electronic design automation sits 18 to 24 months upstream of silicon shipping. A chip being designed on Cadence tools today is a chip that reaches a data centre in 2028. In a week when Asian memory stocks fell 14% on fears about future supply, a record design backlog is the contrary datapoint — the customers are still committing to design cycles for accelerators that do not exist yet.