#Hot Chips

Samsung's In-Memory AI Compute Needs the CPU's Caches Switched Off

The eight-times bandwidth figure from Hot Chips is measured inside the package. Using it costs the host processor its cache, prefetch and out-of-order execution.

1d ago

Samsung presentation slide titled “Progression of Samsung PIM Technology”, charting HBM-PIM proof of concept in 2021 through to LPDDR5X-PIM productisation in 2026

AI Chips

d-Matrix Claims 20x HBM4 Bandwidth Density, Names No Date

A challenger architecture aimed squarely at the wall Micron spent the previous session describing.

6d ago

A d-Matrix slide headed Raptor 3D-DRAM, showing logic dies face-to-face with DRAM over a substrate and a table comparing HBM4 against 3D-DRAM on IO energy, bandwidth and capacity.

AI Chips

SK Hynix's HBM4: 12-High in Production, 16-High in Qualification

One word separates a shipping part from a sample, and the packaging slide being read as an Intel win is a comparison table.

6d ago

An SK hynix slide titled High Bandwidth Memory and Advanced Packaging, showing HBM stacked on a silicon interposer beside a processor with 1,024 IOs across 16 channels.

AI Chips

Samsung's HBM4 Base Die: 4nm Logic, Quadruple Power Density

The layer at the bottom of the memory stack is becoming a logic chip, and it is getting hot faster than the stack above it.

6d ago

A Samsung presentation slide headed High Bandwidth Memory, diagramming the core die and base die roles in an HBM stack with through-silicon vias to a computing die.