IBM's Mainframe Core Executes Arm in Silicon, With 2,792 Instructions

At Hot Chips 2026 on Monday, IBM disclosed a next-generation IBM Z and LinuxONE processor whose every core natively executes two instruction set architectures: z/Architecture, the mainframe ISA it has carried since 1964, and Arm AArch64. Not emulation. Not a bolted-on co-processor. Both decoded in the same core, in hardware.

What was actually disclosed

The part carries 11 IBM Z cores running at 5.7 GHz and above, built on 2nm. Each core gets 36 MB of private L2, backed by a 432 MB virtual L3 and a 3.5 GB virtual L4 — the deep, shared cache hierarchy that is the mainframe's actual architectural signature. Cores are SMT2. A companion AI accelerator carries 16 active AI cores plus one redundant, 96 GB of HBM3e at roughly 4 TB/s, and connects over PCIe Gen6, with IBM claiming up to 4x the TOPS of the previous generation.

What the conventional framing gets wrong

The line this will travel under is "IBM mainframes now run Arm software." Two things are being collapsed into that. The first is stage: this is a disclosure of a future processor at an academic conference. There is no product name, no availability window and no ship date in any open source. Hot Chips is where architectures are described, not where products are launched. The second is the word native. It is scoped by a number IBM printed itself — 2,792 AArch64 instructions implemented. That is a count of what the decoder handles, not a statement that any Arm binary you own will run. A vendor that could claim unconditional Arm compatibility would not publish an instruction count; it would publish a compatibility certification.

Why IBM would do this at all

The mainframe's problem has never been throughput. It is that almost nobody writes new software for it, and the platform's economics depend on workloads that already exist staying where they are. A core that eats Arm binaries in silicon is an attempt to buy back into the software ecosystem the platform lost — at 2nm, with HBM3e inference silicon attached, aimed at customers who want to run modern Linux-and-Arm services next to the transaction engine rather than beside it in another rack.

What to watch

The instruction count is the thing to track. If a later disclosure raises it materially, or IBM publishes a compatibility statement instead of a count, the claim changes character. Until then this is an architecture with an interesting decoder and no delivery date.