Microsoft gave Maia 200 its first full architectural disclosure at Hot Chips on Tuesday afternoon: an 820 mm² die carrying 140 billion transistors on TSMC 3nm, drawing 750 W, rated at 10,000 TFLOPS of FP4, and demonstrated in a configuration of 128 racks and roughly 6,000 chips.
A genuinely large piece of silicon
820 mm² is reticle-class — near the largest a single die can be. The networking is unusual and deliberate: a custom NIC and unified Ethernet with no separate scale-out fabric, eight Ethernet lanes per SoC split across four network planes. Microsoft is betting that one Ethernet-based network can carry both scale-up and scale-out traffic.
What the common framing gets wrong
Two things. The compute figure is FP4: 10 PFLOPS of four-bit math is roughly comparable to OpenAI's 13.4 PFLOP/s of MXFP4, and not comparable to any FP8 or BF16 number. No dense figure was given. But the buried lede is memory, and it points the wrong way for Microsoft. Maia 200 uses HBM3e while the parts it shared an afternoon with use HBM4. Microsoft disclosed bandwidth — 7 TB/s — but not capacity, only the stack count. Quoting 7 TB/s alongside OpenAI's 15.4 TB/s without noting the memory generation is the error to avoid: six stacks of HBM3e is a 2024-generation memory subsystem on a 2026 accelerator, and capacity is the number that decides which models fit.
'Preparing to deploy' is not deployed
Microsoft characterised the part as being readied for Azure. That is a different claim from OpenAI's, made hours later, that Codex is already running on Jalapeño. The 128-rack, 6,000-chip figure is a demonstrated configuration, not an installed fleet.
And a successor may already be in flight
Reporting from earlier in August has Microsoft moving to Maia 300 with a September timeframe. If that holds, Maia 200 is a short-lived generation that arrives with older memory than its peers, still pre-deployment, while the tenant it was partly built for is running its own silicon.